mirror of https://github.com/YosysHQ/yosys.git
16 lines
416 B
Plaintext
16 lines
416 B
Plaintext
read_verilog << EOT
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module tribuf_nested_simple(input [3:0] in1, input [3:0] in2, input [3:0] in3, input sel1, input sel2, input sel3, output [3:0] out1);
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assign out1 = (sel1) ? in1 : ((sel2) ? in2 : 4'bzzzz);
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assign out1 = (sel3) ? in3 : 4'bzzzz;
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endmodule
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EOT
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opt_clean
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tribuf -merge -nested
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# -assert ensures that we won't have
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# multiple drivers (as the first mux is recognized correctly).
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check -assert
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