Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
cf52cf300916d82eaee0194b29d9ae342c0a6d68
yosys/frontends/verilog
T
History
Emil J. Tywoniak 81bbde62ca verilog_parser: silence yynerrs warning
2024-10-15 08:32:55 -04:00
..
.gitignore
Add "make coverage"
2018-08-27 14:22:21 +02:00
const2ast.cc
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
Makefile.inc
Treat all bison warnings as errors in verilog front-end
2020-07-15 11:57:31 +02:00
preproc.cc
set default_nettype to wire for resetall
2022-08-10 13:28:19 +02:00
preproc.h
verilog: save and restore overwritten macro arguments
2021-07-28 21:52:16 -04:00
verilog_frontend.cc
read_verilog: Add missing defaults for flags
2024-05-07 20:25:36 +02:00
verilog_frontend.h
verilog: Squash a memory leak.
2021-06-14 17:07:41 +02:00
verilog_lexer.l
fmt: %t/$time support
2023-08-11 04:46:52 +02:00
verilog_parser.y
verilog_parser: silence yynerrs warning
2024-10-15 08:32:55 -04:00
Powered by Gitea Version: 1.27.2 Page: 94ms Template: 1ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API