mirror of https://github.com/YosysHQ/yosys.git
13 lines
284 B
Python
13 lines
284 B
Python
from pathlib import Path
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from pyosys import libyosys as ys
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__file_dir__ = Path(__file__).absolute().parent
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design = ys.Design()
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design.run_pass(
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["read_verilog", str(__file_dir__.parent / "simple" / "fiedler-cooley.v")]
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)
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design.run_pass("prep")
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design.run_pass(["opt", "-full"])
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