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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-04 03:23:11 +02:00
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cede13a742854cd8f2eee6e4e836d51c15abd2c3
yosys/passes
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History
Emil J cede13a742 Merge pull request #5765 from YosysHQ/emil/muxpack-wide-port
muxpack: fix wide Y port handling
2026-03-31 10:49:39 +00:00
..
cmds
Merge pull request #5724 from abhinavputhran/fix/setundef-respect-selection
2026-03-18 22:53:06 +00:00
equiv
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes
2026-03-04 14:47:57 +00:00
fsm
fsm_detect: add adff detection
2025-11-06 23:29:47 +02:00
hierarchy
hierarchy.cc: Tidying
2025-10-15 09:42:47 +13:00
memory
memory_libmap: Add -force-params
2026-02-20 10:57:00 +00:00
opt
muxpack: fix wide Y port handling
2026-03-19 00:12:49 +01:00
pmgen
Remove .c_str() from log_cmd_error() and log_file_error() parameters
2025-09-16 22:59:08 +00:00
proc
proc_clean: Removing an empty full_case is doing something
2026-01-07 13:10:32 +13:00
sat
sim: cache sigmap in register_output_step_values
2026-03-24 16:10:11 -07:00
techmap
Merge pull request #5764 from YosysHQ/emil/constmap-error
2026-03-23 15:15:04 +00:00
tests
test_cell.cc: Generate .aag for all compatible cells
2025-12-02 14:03:36 +13:00
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