yosys/techlibs at ccfa2fe01cffcc4d23bc989e558bd33addfea58e - yosys - Gitea: Git with a cup of tea

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David Shah 46f6a60d58 xilinx: Add keep attribute where appropriate

Signed-off-by: David Shah <[email protected]>

2019-03-22 13:57:17 +00:00

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Reduce amount of trailing whitespace in code base

2019-02-28 14:58:11 -08:00

Reduce amount of trailing whitespace in code base

2019-02-28 14:58:11 -08:00

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Unify usage of noflatten among architectures

2019-01-04 11:37:25 +01:00

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ecp5: Demote conflicting FF init values to a warning

2019-03-04 11:26:20 +00:00

Reduce amount of trailing whitespace in code base

2019-02-28 14:58:11 -08:00

techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module

2019-02-26 09:40:46 -08:00

Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes

2019-03-12 20:14:18 +01:00

Reduce amount of trailing whitespace in code base

2019-02-28 14:58:11 -08:00

Add link to SF2 / igloo2 macro library guide

2019-03-07 09:08:26 -08:00

xilinx: Add keep attribute where appropriate

2019-03-22 13:57:17 +00:00

.gitignore

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