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luke
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yosys
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ccfa2fe01cffcc4d23bc989e558bd33addfea58e
yosys
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frontends
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ast
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Clifford Wolf
638be461c3
Fix mem2reg handling of memories with upto data ports,
fixes
#888
...
Signed-off-by: Clifford Wolf <
[email protected]
>
2019-03-21 22:21:17 +01:00
..
ast.cc
Improve "read_verilog -dump_vlog[12]" handling of upto ranges
2019-03-21 22:20:16 +01:00
ast.h
Improve read_verilog debug output capabilities
2019-03-21 20:52:29 +01:00
dpicall.cc
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
genrtlil.cc
Improve handling of "full_case" attributes
2019-03-14 17:51:21 +01:00
Makefile.inc
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
simplify.cc
Fix mem2reg handling of memories with upto data ports,
fixes
#888
2019-03-21 22:21:17 +01:00
