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luke
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yosys
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https://github.com/YosysHQ/yosys.git
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cbbd8c0dfd78fd27d6041261a2a7f9502a82cb5a
yosys
/
backends
/
verilog
T
History
Janeczko Jakub
d840a852a9
Fix typo in comment about address collision pattern
2026-08-04 06:44:05 +02:00
..
CMakeLists.txt
Migrate build system to CMake
2026-06-03 08:58:10 +00:00
verilog_backend.cc
Fix typo in comment about address collision pattern
2026-08-04 06:44:05 +02:00
verilog_backend.h
verilog backend: runtime optimization for keyword pool
2026-05-29 17:53:31 +00:00