Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-02 02:57:40 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
cad98bcd89cd9747f3ea9e35eed8d9bbedd64d7a
yosys/passes
T
History
Clifford Wolf 788bd02f97 Fixed FSM mapping for multiple reset-like signals
2014-08-10 12:04:02 +02:00
..
abc
No implicit conversion from IdString to anything else
2014-08-02 18:58:40 +02:00
cmds
Fixed build with gcc-4.6
2014-08-07 22:37:01 +02:00
fsm
Fixed FSM mapping for multiple reset-like signals
2014-08-10 12:04:02 +02:00
hierarchy
More bugfixes related to new RTLIL::IdString
2014-08-02 18:14:21 +02:00
memory
Various improvements in memory_dff pass
2014-08-06 14:31:38 +02:00
opt
Fixed a performance bug in opt_reduce
2014-08-02 15:12:16 +02:00
proc
More cleanups related to RTLIL::IdString usage
2014-08-02 13:19:57 +02:00
sat
Fixed "share" for complex scenarios with never-active cells
2014-08-09 17:07:20 +02:00
techmap
Implemented recursive techmap
2014-08-03 12:40:43 +02:00
tests
More cleanups related to RTLIL::IdString usage
2014-08-02 13:19:57 +02:00
Powered by Gitea Version: 1.27.2 Page: 1422ms Template: 9ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API