Clifford Wolf cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions

2014-07-31 16:38:54 +02:00

..

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00

ilang_frontend.cc

Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

2014-07-31 13:19:47 +02:00

ilang_frontend.h

Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

2014-07-31 13:19:47 +02:00

lexer.l

Added wire->upto flag for signals such as "wire [0:7] x;"

2014-07-28 12:12:13 +02:00

Makefile.inc

Added "make PRETTY=1"

2014-07-24 17:15:01 +02:00

parser.y

Renamed port access function on RTLIL::Cell, added param access functions

2014-07-31 16:38:54 +02:00