This website requires JavaScript.
Explore
Help
Sign In
luke
/
yosys
Watch
1
Star
0
Fork
0
mirror of
https://github.com/YosysHQ/yosys.git
synced
2026-10-07 02:23:09 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
ca8f8e30f20fd48127003486f1701ac17fd35aa6
yosys
/
techlibs
T
History
Clifford Wolf
ca8f8e30f2
Improvements in synth_greenpak4, added -part option
2016-03-21 09:44:52 +01:00
..
common
Progress in cell library documentation
2016-02-01 13:58:10 +01:00
greenpak4
Improvements in synth_greenpak4, added -part option
2016-03-21 09:44:52 +01:00
ice40
Work around DDR dout sim glitches in ice40 SB_IO sim model
2016-02-07 11:19:48 +01:00
xilinx
Added black box modules for all the 7-series design elements (as listed in ug953)
2016-03-19 11:09:10 +01:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
