mirror of https://github.com/YosysHQ/yosys.git
34 lines
629 B
Plaintext
34 lines
629 B
Plaintext
read_verilog -specify << EOT
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module top(input a, b, output o);
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wire c, d;
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bb bb1 (.a (a), .b (b), .o (c));
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wb wb1 (.a (a), .b (b), .o (d));
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some_mod some_inst (.a (c), .b (d), .o (o));
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endmodule
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(* blackbox *)
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module bb(input a, b, output o);
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assign o = a | b;
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specify
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(a => o) = 1;
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endspecify
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endmodule
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(* whitebox *)
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module wb(input a, b, output o);
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assign o = a ^ b;
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endmodule
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module some_mod(input a, b, output o);
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assign o = a & b;
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endmodule
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EOT
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select top
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select -assert-count 0 t:$anyseq
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select -assert-count 2 =t:?b
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cutpoint -blackbox =*
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select -assert-count 2 t:$anyseq
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select -assert-count 2 t:?b
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