Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-02 11:07:41 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
c997a77014b5d8dbfb24e77bb8157454619ea366
yosys/backends
T
History
Eddie Hung 8fe0a961b3 Merge remote-tracking branch 'origin/clifford/whitebox' into xaig
2019-04-18 09:00:06 -07:00
..
aiger
Fix $anyseq warning and cleanup
2019-04-17 16:03:29 -07:00
blif
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
btor
Add support for memory initialization to write_btor
2019-03-23 14:40:01 +01:00
edif
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
firrtl
Refine memory support to deal with general Verilog memory definitions.
2019-04-01 15:02:12 -07:00
ilang
Fix a syntax bug in ilang backend related to process case statements
2019-03-14 17:50:20 +01:00
intersynth
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
json
Merge pull request #591 from hzeller/virtual-override
2018-08-15 14:05:38 +02:00
protobuf
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
simplec
Fix typographical and grammatical errors and inconsistencies.
2019-01-02 13:12:17 +00:00
smt2
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
smv
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
spice
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
table
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
verilog
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
Powered by Gitea Version: 1.27.2 Page: 2674ms Template: 3ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API