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luke
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yosys
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https://github.com/YosysHQ/yosys.git
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2026-09-04 11:29:42 +02:00
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c7f5091c2fac374c4e48cd9736c2727d65acdcf9
yosys
/
techlibs
/
common
T
History
Eddie Hung
f7a9769c14
Merge remote-tracking branch 'origin/master' into xaig
2019-06-12 08:50:39 -07:00
..
.gitignore
…
adff2dff.v
…
cellhelp.py
…
cells.lib
…
cmp2lut.v
cmp2lut: new techmap pass.
2019-01-02 07:53:31 +00:00
dff2ff.v
…
gate2lut.v
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
2018-12-05 17:13:27 +00:00
Makefile.inc
cmp2lut: new techmap pass.
2019-01-02 07:53:31 +00:00
pmux2mux.v
…
prep.cc
Add "wreduce -keepdc",
fixes
#1016
2019-05-20 15:36:13 +02:00
simcells.v
…
simlib.v
Improve $specrule interface
2019-04-23 22:57:10 +02:00
synth.cc
Merge remote-tracking branch 'origin/master' into xaig
2019-06-12 08:50:39 -07:00
techmap.v
…
