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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 19:19:48 +02:00
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c7d71f436d822bbbe3cda118591ed2b33eae3a7f
yosys/techlibs/intel_alm/common
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Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes.
Fixes #2058.
2020-05-19 01:42:40 +02:00
..
alm_map.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
alm_sim.v
intel_alm: Documentation improvements
2020-04-21 19:38:15 +02:00
arith_alm_map.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
bram_m10k_map.v
intel_alm: direct LUTRAM cell instantiation
2020-05-07 21:03:13 +02:00
bram_m10k.txt
synth_intel_alm: alternative synthesis for Intel FPGAs
2020-04-15 11:40:41 +02:00
bram_m20k_map.v
synth_intel_alm: alternative synthesis for Intel FPGAs
2020-04-15 11:40:41 +02:00
bram_m20k.txt
synth_intel_alm: alternative synthesis for Intel FPGAs
2020-04-15 11:40:41 +02:00
dff_map.v
intel_alm: Documentation improvements
2020-04-21 19:38:15 +02:00
dff_sim.v
intel_alm: Documentation improvements
2020-04-21 19:38:15 +02:00
lutram_mlab.txt
intel_alm: direct LUTRAM cell instantiation
2020-05-07 21:03:13 +02:00
megafunction_bb.v
intel_alm: direct LUTRAM cell instantiation
2020-05-07 21:03:13 +02:00
mem_sim.v
intel_alm: direct LUTRAM cell instantiation
2020-05-07 21:03:13 +02:00
quartus_rename.v
intel_alm: direct LUTRAM cell instantiation
2020-05-07 21:03:13 +02:00
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