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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-01 18:47:29 +02:00
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c7cf9415f8ad2cde0eae5020ea498d82ad72f00a
yosys/frontends
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Miodrag Milanovic c228cb74d6 Update verific version
2020-10-30 08:32:59 +01:00
..
aiger
Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().
2020-06-19 15:48:58 +00:00
ast
Merge pull request #2378 from udif/pr_dollar_high_low
2020-10-01 18:17:36 +02:00
blif
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
json
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
liberty
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
rpc
Fix argument handling in connect_rpc
2020-10-19 13:40:57 +02:00
rtlil
Replace "ILANG" with "RTLIL" everywhere.
2020-08-26 17:29:32 +00:00
verific
Update verific version
2020-10-30 08:32:59 +01:00
verilog
Ignore empty parameters in Verilog module instantiations
2020-10-01 18:27:16 +02:00
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