mirror of https://github.com/YosysHQ/yosys.git
18 lines
390 B
Systemverilog
18 lines
390 B
Systemverilog
module opt_compact_prefix_sub16 (
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input logic [31:0] disable_in,
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input logic [31:0] data_in,
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output logic [31:0] mask
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);
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always_comb begin
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mask = '0;
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for (int I = 16, indx = 16; I > 0; I--) begin
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if (disable_in[I-1]) begin
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mask[I-1] = 1'b0;
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end else begin
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mask[I-1] = data_in[indx-1];
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indx = indx - 1;
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end
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end
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end
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endmodule
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