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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 11:59:46 +02:00
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c7afbd9d8efcf3045d9e4244600ce8d8e0d40b6d
yosys/techlibs/xilinx
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Clifford Wolf b17d6531c8 Added "make PRETTY=1"
2014-07-24 17:15:01 +02:00
..
example_mojo_counter
…
example_sim_counter
Fixed xilinx/example_sim_counter test bench
2013-11-24 17:55:46 +01:00
example_zed_counter
…
cells.v
Added more generic _TECHMAP_ wire mechanism to techmap pass
2013-11-23 15:58:06 +01:00
Makefile.inc
Added "make PRETTY=1"
2014-07-24 17:15:01 +02:00
synth_xilinx.cc
Added "techmap -share_map" option
2013-11-24 19:50:25 +01:00
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