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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 20:12:09 +02:00
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c6e112686ca93403847a144ded8eefceef674c42
yosys/techlibs/quicklogic/common
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N. Engelhardt 98769010af synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
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cells_sim.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
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