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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-30 01:48:17 +02:00
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c50afc4246d552db079aec303b0d79ae92107a67
yosys/techlibs
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Clifford Wolf 5f1fea08d5 Add inout ports to cells_xtra.v
Signed-off-by: Clifford Wolf <[email protected]>
2018-10-04 11:30:55 +02:00
..
achronix
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
common
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
coolrunner2
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
easic
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
ecp5
ecp5: Don't map ROMs to DRAM
2018-10-01 18:34:41 +01:00
gowin
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
greenpak4
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
ice40
Add iCE40 SB_SPRAM256KA simulation model
2018-09-10 11:57:24 +02:00
intel
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
xilinx
Add inout ports to cells_xtra.v
2018-10-04 11:30:55 +02:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
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