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27 lines
487 B
Plaintext
27 lines
487 B
Plaintext
read_rtlil <<RTLIL
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autoidx 1
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module \top
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wire input 1 \a
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wire output 1 \y
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wire \n0
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wire \n1
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wire \n2
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cell $_NOT_ \u0
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connect \A \a
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connect \Y \n0
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end
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connect \n1 \n0
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connect \n2 \n1
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connect \y \n2
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end
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RTLIL
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select -assert-count 5 o:y %ci1
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select -assert-count 1 o:y %ci1 t:$_NOT_ %i
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select -assert-count 0 o:y %ci1 i:a %i
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select -assert-count 6 o:y %ci2
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select -assert-count 2 i:a %co1
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select -assert-count 6 i:a %co2
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select -assert-count 1 i:a %co2 o:y %i
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