Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 18:13:40 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
c3807b4137cfdb0aa4e2db85d51abcd7bdeda247
yosys/passes
T
History
Emil J. Tywoniak 7a09c32040 signorm: disable passes that use rewrite_sigspecs
2026-09-17 14:13:57 +02:00
..
cmds
signorm: disable passes that use rewrite_sigspecs
2026-09-17 14:13:57 +02:00
equiv
signorm: disable passes that use rewrite_sigspecs
2026-09-17 14:13:57 +02:00
fsm
opt_clean: move unused_bits analysis to kernel/unused_bits.h
2026-08-12 11:42:50 +02:00
hierarchy
flatten: skip $input_port cells in template module
2026-09-17 14:13:57 +02:00
memory
Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
opt
signorm: disable in passes that use swap_names
2026-09-17 14:13:57 +02:00
pmgen
Migrate build system to CMake
2026-06-03 08:58:10 +00:00
proc
Merge branch 'main' into nella/latch-toggle
2026-07-08 11:41:08 +02:00
sat
signorm: disable passes that use rewrite_sigspecs
2026-09-17 14:13:57 +02:00
techmap
signorm: disable passes that use rewrite_sigspecs
2026-09-17 14:13:57 +02:00
tests
End of file fix
2026-06-23 07:23:41 +02:00
CMakeLists.txt
Migrate build system to CMake
2026-06-03 08:58:10 +00:00
Powered by Gitea Version: 1.27.2 Page: 86ms Template: 3ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API