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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-07 18:43:22 +02:00
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c35db8c19e2d0c84e5947bc23345a87f3d4afd00
yosys/passes
T
History
Clifford Wolf c35db8c19e Disabled "Skipping blackbox module" msg in show command
2015-10-23 20:11:05 +02:00
..
cmds
Disabled "Skipping blackbox module" msg in show command
2015-10-23 20:11:05 +02:00
equiv
Also merge $equiv cells in equiv_struct
2015-10-23 15:26:58 +02:00
fsm
Do not detect fsm state registers with init attribute
2015-09-21 11:54:00 +02:00
hierarchy
Spell check (by Larry Doolittle)
2015-08-14 10:56:05 +02:00
memory
Bugfix in bram read-enable code
2015-09-25 14:22:33 +02:00
opt
Bugfixes in handling of "keep" attribute on wires
2015-10-15 14:57:28 +02:00
proc
Re-created command-reference-manual.tex, copied some doc fixes to online help
2015-08-14 11:27:19 +02:00
sat
Added sat -show-regs, -show-public, -show-all
2015-08-18 17:14:30 +02:00
techmap
Fixed "flatten" for unconnected inout ports
2015-10-13 10:30:23 +02:00
tests
Added "test_cell -noeval"
2015-09-25 17:27:18 +02:00
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