yosys/techlibs at c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1 - yosys - Gitea: Git with a cup of tea

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Miodrag Milanović b4d7650548 Merge branch 'master' into mmicko/efinix

2019-10-18 10:54:28 +02:00

..

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

make note that it is for latch mode

2019-09-18 17:48:16 +02:00

Missing (* mul2dsp *) for sliceB

2019-09-27 14:21:47 -07:00

Fix spacing

2019-08-06 16:47:55 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

ecp5: Add ECLKBRIDGECS blackbox

2019-10-11 14:50:33 +01:00

FF should be initialized to 0

2019-10-04 13:27:10 +02:00

Fix formatting for msys2 mingw build using GetSize

2019-08-01 17:27:34 +02:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Rename abc_* names/attributes to more precisely be abc9_*

2019-10-04 11:04:10 -07:00

techlibs/intel: Clean up Makefile

2019-08-05 11:22:11 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

xilinx: Add simulation model for IBUFG.

2019-10-10 13:16:03 +02:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00