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luke
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yosys
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https://github.com/YosysHQ/yosys.git
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c1921b45619fbca4cbcafe3cd9cfdc0fe29e251c
yosys
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tests
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arch
T
History
Pepijn de Vos
8226f2db0b
ALU sim tweaks
2019-10-24 13:39:43 +02:00
..
anlogic
Common memory test now shared
2019-10-18 12:33:35 +02:00
common
fixed error
2019-10-18 13:15:36 +02:00
ecp5
Common memory test now shared
2019-10-18 12:33:35 +02:00
efinix
Common memory test now shared
2019-10-18 12:33:35 +02:00
gowin
ALU sim tweaks
2019-10-24 13:39:43 +02:00
ice40
Common memory test now shared
2019-10-18 12:33:35 +02:00
xilinx
Common memory test now shared
2019-10-18 12:33:35 +02:00
run-test.sh
Add simcells.v, simlib.v, and some output
2019-06-27 11:13:49 -07:00
