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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-02 02:57:40 +02:00
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c1921b45619fbca4cbcafe3cd9cfdc0fe29e251c
yosys/frontends/verilog
T
History
Clifford Wolf e84cedfae4 Use "(id)" instead of "id" for types as temporary hack
Signed-off-by: Clifford Wolf <[email protected]>
2019-10-14 05:24:31 +02:00
..
.gitignore
Add "make coverage"
2018-08-27 14:22:21 +02:00
const2ast.cc
Fix handling of z_digit "?" and fix optimization of cmp with "z"
2019-09-13 13:39:39 +02:00
Makefile.inc
Read bigger Verilog files.
2019-05-18 14:20:30 +03:00
preproc.cc
Support SystemVerilog `` extension for macros
2018-05-17 00:09:56 -04:00
verilog_frontend.cc
Add "read_verilog -pwires" feature, closes #1106
2019-06-19 14:38:50 +02:00
verilog_frontend.h
Add specify parser
2019-04-23 21:36:59 +02:00
verilog_lexer.l
Fix lexing of integer literals without radix
2019-09-13 10:19:58 +02:00
verilog_parser.y
Use "(id)" instead of "id" for types as temporary hack
2019-10-14 05:24:31 +02:00
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