Clifford Wolf 0e7901e45c Merge pull request #941 from Wren6991/sim_lib_io_clke ... ice40 cells_sim.v: update clock enable behaviour based on hardware experiments		2019-04-22 09:11:13 +02:00
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achronix	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
anlogic	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
common	Merge pull request #772 from whitequark/synth_lut	2019-01-02 15:44:57 +01:00
coolrunner2	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
easic	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
ecp5	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
gowin	Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master	2019-04-22 09:09:27 +02:00
greenpak4	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
ice40	ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware experiments	2019-04-21 21:40:11 +01:00
intel	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
sf2	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
xilinx	Re-added clean after techmap in synth_xilinx	2019-04-22 09:03:11 +02:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00