yosys/tests/techmap
Marcelina Kościelnicka 7ed9d18907 dfflibmap: Refactor to use dfflegalize internally. 2020-07-09 18:51:03 +02:00
..
.gitignore
abc9.ys
aigmap.ys
autopurge.ys
clkbufmap.ys clkbufmap: improve input pad handling. 2020-07-09 18:48:01 +02:00
cmp2lcu.ys +/cmp2lcu.v to work efficiently for fully/partially constant inputs 2020-04-03 14:28:22 -07:00
dff2dffs.ys Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00
dffinit.ys dffinit: Avoid setting init parameter to zero-length value. 2020-04-14 19:52:19 +02:00
dfflegalize_adff.ys clk2fflogic: Consistently treat async control signals as negative hold. 2020-07-09 18:12:47 +02:00
dfflegalize_adff_init.ys clk2fflogic: Consistently treat async control signals as negative hold. 2020-07-09 18:12:47 +02:00
dfflegalize_adlatch.ys clk2fflogic: Consistently treat async control signals as negative hold. 2020-07-09 18:12:47 +02:00
dfflegalize_adlatch_init.ys clk2fflogic: Consistently treat async control signals as negative hold. 2020-07-09 18:12:47 +02:00
dfflegalize_dff.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_dff_init.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_dffsr.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_dffsr_init.ys clk2fflogic: Consistently treat async control signals as negative hold. 2020-07-09 18:12:47 +02:00
dfflegalize_dlatch.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_dlatch_const.ys dfflegalize: Add special support for const-D latches. 2020-07-09 18:11:32 +02:00
dfflegalize_dlatch_init.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_dlatchsr.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_dlatchsr_init.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_inv.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_mince.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_minsrst.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_sr.ys clk2fflogic: Consistently treat async control signals as negative hold. 2020-07-09 18:12:47 +02:00
dfflegalize_sr_init.ys clk2fflogic: Consistently treat async control signals as negative hold. 2020-07-09 18:12:47 +02:00
dfflibmap-sim.v dfflibmap: Refactor to use dfflegalize internally. 2020-07-09 18:51:03 +02:00
dfflibmap.lib dfflibmap: Refactor to use dfflegalize internally. 2020-07-09 18:51:03 +02:00
dfflibmap.ys dfflibmap: Refactor to use dfflegalize internally. 2020-07-09 18:51:03 +02:00
extractinv.ys
iopadmap.ys iopadmap: Fix z assignment to inout port 2020-04-02 18:15:04 +02:00
mem_simple_4x1_cells.v
mem_simple_4x1_map.v
mem_simple_4x1_runtest.sh
mem_simple_4x1_tb.v
mem_simple_4x1_uut.v
recursive.v
recursive_map.v
recursive_runtest.sh
run-test.sh
shiftx2mux.ys
techmap_replace.ys techmap: Fix cell names with _TECHMAP_REPLACE_.* 2020-03-23 11:17:07 +01:00
wireinit.ys
zinit.ys Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00