Sahand Kashani c0b2a9af2e Add fileinfo to firrtl backend for assignments and non-instance cells

2020-03-21 12:54:23 +01:00

..

aiger

xaiger: remove some unnecessary operations ...

2020-03-06 10:51:47 -08:00

blif

RTLIL::S{0,1} -> State::S{0,1}

2019-08-07 11:12:38 -07:00

btor

Use cell name for btor bad state props when it is a public name

2019-11-14 11:57:38 +01:00

edif

edif: more resilience to mismatched port connection sizes.

2020-02-06 18:45:03 +01:00

firrtl

Add fileinfo to firrtl backend for assignments and non-instance cells

2020-03-21 12:54:23 +01:00

ilang

RTLIL::S{0,1} -> State::S{0,1}

2019-08-07 11:12:38 -07:00

intersynth

substr() -> compare()

2019-08-07 12:20:08 -07:00

json

json: Change compat mode to directly emit ints <= 32 bits

2020-02-09 01:01:18 -08:00

protobuf

Add aiger and protobuf backends binary support

2019-09-28 09:51:48 +02:00

simplec

Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs

2019-08-06 04:47:55 +02:00

smt2

Merge pull request #1768 from boqwxp/smt2_cleanup

2020-03-16 13:49:10 +01:00

smv

substr() -> compare()

2019-08-07 12:20:08 -07:00

spice

Add "whitebox" attribute, add "read_verilog -wb"

2019-04-18 17:45:47 +02:00

table

Add "whitebox" attribute, add "read_verilog -wb"

2019-04-18 17:45:47 +02:00

verilog

specify: system timing checks to accept min:typ:max triple

2020-02-13 12:42:15 -08:00