Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 18:13:40 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
c0a156bcb43bb0bb42eb3f2d94c12cda9ca5ee37
yosys/passes
T
History
Miodrag Milanovic c0a156bcb4 Error detection for co-simulation
2022-02-04 11:11:36 +01:00
..
cmds
bugpoint: avoid infinite loop between -connections and -wires.
2021-12-15 08:17:02 +00:00
equiv
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
fsm
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
hierarchy
verilog: use derived module info to elaborate cell connections
2021-10-25 18:25:50 -07:00
memory
memory_share: Fix SAT-based sharing for wide ports.
2021-12-20 18:40:14 +01:00
opt
opt_dff: fix sequence point copy paste bug
2022-01-04 18:18:08 +01:00
pmgen
Make it work on all
2021-11-05 10:51:58 +01:00
proc
proc_dff: Emit $aldff.
2021-10-27 14:14:24 +02:00
sat
Error detection for co-simulation
2022-02-04 11:11:36 +01:00
techmap
sta: very crude static timing analysis pass
2021-11-25 17:20:27 +01:00
tests
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
Powered by Gitea Version: 1.27.2 Page: 146ms Template: 6ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API