Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-05 19:36:55 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
c0779f488afdbb2e789ea5ede63a3a7e720fc0e4
yosys/techlibs/quicklogic
T
History
Miodrag Milanovic 4a7878b17f Fixing couple more conversion errors
2026-05-14 15:58:58 +02:00
..
common
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
pp3
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
qlf_k6n10f
Drop timestamp in generate_bram_types_sim.py
2024-10-30 08:47:18 +01:00
.gitignore
add dsp inference
2023-12-04 15:52:02 +01:00
Makefile.inc
add ioff inference for qlf_k6n10f
2025-01-24 21:17:15 +01:00
ql_bram_merge.cc
Refactored uses of log_id()
2026-05-08 20:59:24 -07:00
ql_bram_types.cc
Refactored uses of log_id()
2026-05-08 20:59:24 -07:00
ql_dsp_io_regs.cc
Refactored uses of log_id()
2026-05-08 20:59:24 -07:00
ql_dsp_macc.cc
Fixing couple more conversion errors
2026-05-14 15:58:58 +02:00
ql_dsp_macc.pmg
ql_dsp_macc: Tune DSP inference code
2023-12-04 15:52:02 +01:00
ql_dsp_simd.cc
Refactored uses of log_id()
2026-05-08 20:59:24 -07:00
ql_ioff.cc
Remove .c_str() from parameters to log_debug()
2025-09-23 19:10:33 +12:00
synth_quicklogic.cc
Add check before flatten in synth_*.
2026-05-05 14:06:58 +02:00
Powered by Gitea Version: 1.27.2 Page: 1116ms Template: 49ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API