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yosys/passes
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Clifford Wolf 1f64b34c64 Add "add -mod" 
Signed-off-by: Clifford Wolf <[email protected]>
2019-09-20 10:27:17 +02:00
..
cmds
Add "add -mod"
2019-09-20 10:27:17 +02:00
equiv
Add equiv_opt -multiclock
2019-09-11 13:55:59 +01:00
fsm
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
hierarchy
Adopt @cliffordwolf's suggestion
2019-09-03 12:18:50 -07:00
memory
stoi -> atoi
2019-08-07 11:09:17 -07:00
opt
Revert "SigSet<Cell*> to use stable compare class"
2019-09-13 09:49:15 -07:00
pmgen
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
2019-09-18 12:40:08 -07:00
proc
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
sat
Revert "SigSet<Cell*> to use stable compare class"
2019-09-13 09:49:15 -07:00
techmap
Add techmap_autopurge attribute, fixes #1381
2019-09-19 20:00:52 +02:00
tests
Document (* gentb_skip *) attr for test_autotb
2019-09-18 12:41:35 -07:00