yosys/tests/arch at bfacaddca8a2e113e4bc3d6177612ccdba1555c8 - yosys - Gitea: Git with a cup of tea

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gatecat b6467f0801 fabulous: Allow adding extra custom prims and map rules

Signed-off-by: gatecat <[email protected]>

2022-11-17 13:34:58 +01:00

..

anlogic: support BRAM mapping

2021-12-17 20:28:22 +08:00

Allow initial blocks to be disabled during tests

2021-11-13 21:53:25 +01:00

ecp5: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

efinix: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

fabulous: Allow adding extra custom prims and map rules

2022-11-17 13:34:58 +01:00

gatemate: Add test for LUT tree mapping

2022-06-27 10:09:48 +01:00

gowin: Fix LUT RAM inference, add more models.

2022-02-09 09:04:34 +01:00

Reenable existing equiv_opt tests

2022-10-07 16:04:51 +02:00

Reenable existing equiv_opt tests

2022-10-07 16:04:51 +02:00

iopadmap: Add native support for negative-polarity output enable.

2021-11-09 15:40:16 +01:00

nexus: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

quicklogic: ABC9 synthesis

2021-04-17 20:54:58 +02:00

Fix tests for check in equiv_opt

2022-10-07 16:04:51 +02:00

run-test.sh

Add default assignments to SB_LUT4

2021-04-20 12:46:21 +02:00