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luke
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yosys
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https://github.com/YosysHQ/yosys.git
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bf7d36627e
yosys
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passes
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hierarchy
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Eddie Hung
6a52897aee
sigmap(wire) should inherit port_output status of POs
2019-11-22 16:48:11 -08:00
..
Makefile.inc
Rename "singleton" pass to "uniquify"
2017-08-20 12:31:50 +02:00
hierarchy.cc
Adopt @cliffordwolf's suggestion
2019-09-03 12:18:50 -07:00
submod.cc
sigmap(wire) should inherit port_output status of POs
2019-11-22 16:48:11 -08:00
uniquify.cc
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00