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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 03:13:21 +02:00
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bd65e67d8a0ecc71ae0b5df56799e25dd5f2d99a
yosys/passes
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History
Clifford Wolf bd65e67d8a Improvements in satgen undef handling
2013-11-25 15:12:01 +01:00
..
abc
Updated abc
2013-11-21 22:39:10 +01:00
cmds
Renamed "placeholder" to "blackbox"
2013-11-22 15:01:12 +01:00
extract
Automatically run "proc" on extract map files
2013-07-24 20:19:08 +02:00
fsm
Added detection for endless recursion in fsm_detect pass
2013-10-30 00:47:58 +01:00
hierarchy
Remove auto_wire framework (smarter than the verilog standard)
2013-11-24 17:29:11 +01:00
memory
Fixed help message typo (memory pass)
2013-10-30 00:47:31 +01:00
opt
Cleanups and bugfixes in response to new internal cell checker
2013-11-11 00:39:45 +01:00
proc
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
sat
Improvements in satgen undef handling
2013-11-25 15:12:01 +01:00
scc
fixed typos
2013-03-18 07:28:31 +01:00
submod
Renamed opt_rmunused to opt_clean
2013-06-05 07:07:31 +02:00
techmap
Using simplemap mappers from techmap
2013-11-24 23:31:14 +01:00
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