yosys/backends/firrtl at bd523abef5babcc16fbdd67dbf868bd601acaced - yosys - Gitea: Git with a cup of tea

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Jim Lawson 73b87e7807 Refine memory support to deal with general Verilog memory definitions.

2019-04-01 15:02:12 -07:00

..

.gitignore

Progress in FIRRTL back-end

2016-11-18 00:32:35 +01:00

firrtl.cc

Refine memory support to deal with general Verilog memory definitions.

2019-04-01 15:02:12 -07:00

Makefile.inc

Added first draft of FIRRTL back-end

2016-11-17 23:36:47 +01:00

test.sh

More progress on Firrtl backend.

2017-02-13 11:17:53 -08:00

test.v

More progress on Firrtl backend.

2017-02-13 11:17:53 -08:00