luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-02 02:57:40 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
bc66dfd9ea31f79f97e43f6b48d775245b47cdf4
yosys/tests/fmt
T
History
Catherine fc5ff7a265 cxxrtl: always lazily format print messages. 
This is mostly useful for collecting coverage for the future `$check`
cell, where, depending on the flavor, formatting a message may not be
wanted even for a failed assertion.
2024-01-19 18:55:23 +00:00
..
fuzz
fmt: merge fuzzers since we don't rely on BigInteger logic
2023-08-11 04:46:52 +02:00
.gitignore
fmt: add tests for Verilog round trip of format expressions.
2023-08-11 04:46:52 +02:00
always_comb_tb.cc
cxxrtl: include iostream when prints are used
2023-08-17 07:08:22 +02:00
always_comb_tb.v
cxxrtl: store comb $print cell last EN/ARGS in module
2023-08-11 04:46:52 +02:00
always_comb.v
cxxrtl: WIP: adjust comb display cells to only fire on change
2023-08-11 04:46:52 +02:00
always_display.v
fmt: add tests for Verilog round trip of format expressions.
2023-08-11 04:46:52 +02:00
always_full_tb.cc
cxxrtl: always lazily format print messages.
2024-01-19 18:55:23 +00:00
always_full_tb.v
verilog_backend: emit sync $print cells with same triggers together
2023-08-11 04:46:52 +02:00
always_full.v
verilog_backend: emit sync $print cells with same triggers together
2023-08-11 04:46:52 +02:00
display_lm_tb.cc
cxxrtl: include iostream when prints are used
2023-08-17 07:08:22 +02:00
display_lm.v
fmt: rudimentary %m support (= %l)
2023-08-11 04:46:52 +02:00
initial_display.v
fmt: format %t consistently at initial
2023-08-11 04:46:52 +02:00
roundtrip_tb.v
fmt: add tests for Verilog round trip of format expressions.
2023-08-11 04:46:52 +02:00
roundtrip.v
fmt: add tests for Verilog round trip of format expressions.
2023-08-11 04:46:52 +02:00
run-test.sh
Merge pull request #3887 from kivikakk/env-bash
2023-12-18 16:33:35 +01:00