mirror of https://github.com/YosysHQ/yosys.git
19 lines
319 B
Systemverilog
19 lines
319 B
Systemverilog
module memtest05(clk, addr, wdata, rdata, wen);
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input clk;
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input [1:0] addr;
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input [7:0] wdata;
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output reg [7:0] rdata;
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input [3:0] wen;
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reg [7:0] mem [0:3];
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integer i;
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always @(posedge clk) begin
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for (i = 0; i < 4; i = i+1)
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if (wen[i]) mem[addr][i*2 +: 2] <= wdata[i*2 +: 2];
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rdata <= mem[addr];
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end
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endmodule
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