yosys/techlibs at bbab6086918f8af3a8a09c2be56208fc29ef7068 - yosys - Gitea: Git with a cup of tea

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Eddie Hung bbab608691 Remove SRL* delays from cells_sim.v

2019-08-20 18:14:40 -07:00

..

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

anlogic : Fix alu mapping

2019-08-03 14:47:33 +02:00

Reformat so it shows up/looks nice when "help $alu" and "help $alu+"

2019-08-09 12:33:39 -07:00

Fix spacing

2019-08-06 16:47:55 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro

2019-08-19 09:56:17 -07:00

Fix formatting for msys2 mingw build using GetSize

2019-08-01 17:27:34 +02:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Merge pull request #1304 from YosysHQ/eddie/abc9_refactor

2019-08-20 11:59:31 -07:00

techlibs/intel: Clean up Makefile

2019-08-05 11:22:11 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Remove SRL* delays from cells_sim.v

2019-08-20 18:14:40 -07:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00