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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 11:18:31 +02:00
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baddb017fe5eb72fbb65d6f89553dc2341663613
yosys/passes
T
History
Clifford Wolf 716dbc9274 Revert 90be0d8 as it causes endless loops for some designs
2017-10-14 11:57:25 +02:00
..
cmds
Add blackbox command
2017-10-04 18:30:42 +02:00
equiv
Fix equiv_simple, old behavior now available with "equiv_simple -short"
2017-04-28 18:57:53 +02:00
fsm
Remove some dead code from fsm_map
2017-08-21 15:02:16 +02:00
hierarchy
Rename "singleton" pass to "uniquify"
2017-08-20 12:31:50 +02:00
memory
Typo fix.
2016-09-08 10:57:16 +03:00
opt
Revert 90be0d8 as it causes endless loops for some designs
2017-10-14 11:57:25 +02:00
proc
Add src attribute to extra cells generated by proc_dlatch
2017-09-09 10:18:08 +02:00
sat
Rename "singleton" pass to "uniquify"
2017-08-20 12:31:50 +02:00
techmap
Rewrite ABC output to include proper net names in timing report
2017-10-10 13:32:58 +02:00
tests
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
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