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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 11:59:46 +02:00
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bac1e65a9cecf9a53292f28554f857e4dd3ff4dd
yosys/backends
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History
Eddie Hung 07feedfa73 write_xaiger: get rid of external_bits dict
2020-01-02 15:32:58 -08:00
..
aiger
write_xaiger: get rid of external_bits dict
2020-01-02 15:32:58 -08:00
blif
…
btor
Use cell name for btor bad state props when it is a public name
2019-11-14 11:57:38 +01:00
edif
…
firrtl
Merge pull request #1258 from YosysHQ/eddie/cleanup
2019-08-10 09:52:14 +02:00
ilang
…
intersynth
substr() -> compare()
2019-08-07 12:20:08 -07:00
json
…
protobuf
Add aiger and protobuf backends binary support
2019-09-28 09:51:48 +02:00
simplec
…
smt2
Bugfix in smtio vcd handling of $-identifiers
2019-10-23 00:04:34 +02:00
smv
substr() -> compare()
2019-08-07 12:20:08 -07:00
spice
…
table
…
verilog
write_verilog: add -extmem option, to write split memory init files.
2019-11-18 01:27:21 +00:00
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