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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 18:13:40 +02:00
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b7adf4c7a0d0f561d08d7e4dcf66b4e651596318
yosys/backends
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Ahmed Irfan 9a689f33a5 verilog default options pull
shift operator width issues
2014-01-17 19:32:35 +01:00
..
autotest
Fixed gentb_constant handling in autotest backend
2013-12-04 09:09:42 +01:00
blif
Added "top" attribute to mark top module in hierarchy
2013-11-24 05:03:43 +01:00
btor
verilog default options pull
2014-01-17 19:32:35 +01:00
edif
Replaced RTLIL::Const::str with generic decoder method
2013-12-04 14:14:05 +01:00
ilang
Updated manual/command-reference-manual.tex
2013-12-28 12:14:47 +01:00
intersynth
Renamed "placeholder" to "blackbox"
2013-11-22 15:01:12 +01:00
spice
Added "top" attribute to mark top module in hierarchy
2013-11-24 05:03:43 +01:00
verilog
Added support for non-const === and !== (for miter circuits)
2013-12-27 14:20:15 +01:00
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