mirror of https://github.com/YosysHQ/yosys.git
60 lines
1.0 KiB
Verilog
60 lines
1.0 KiB
Verilog
// Narrow-width test designs for SAT equivalence (4-bit to keep SAT fast)
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module equiv_add3(
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input [3:0] a, b, c,
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output [3:0] y
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);
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assign y = a + b + c;
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endmodule
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module equiv_add4(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a + b + c + d;
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endmodule
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module equiv_add5(
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input [3:0] a, b, c, d, e,
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output [3:0] y
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);
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assign y = a + b + c + d + e;
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endmodule
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module equiv_add8(
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input [3:0] a, b, c, d, e, f, g, h,
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output [3:0] y
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);
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assign y = a + b + c + d + e + f + g + h;
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endmodule
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module equiv_signed(
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input signed [3:0] a, b, c, d,
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output signed [5:0] y
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);
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assign y = a + b + c + d;
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endmodule
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module equiv_mixed_w(
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input [1:0] a,
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input [3:0] b,
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input [5:0] c,
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output [5:0] y
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);
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assign y = a + b + c;
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endmodule
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module equiv_repeated(
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input [3:0] a,
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output [3:0] y
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);
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assign y = a + a + a + a;
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endmodule
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module equiv_1bit_wide(
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input a, b, c, d,
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output [3:0] y
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);
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assign y = a + b + c + d;
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endmodule
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