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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-01 18:47:29 +02:00
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b64b38eea2e9a7de30d6045f069c86bf4446134f
yosys/techlibs/common
T
History
Clifford Wolf b64b38eea2 Renamed $lut ports to follow A-Y naming scheme
2014-08-15 14:18:40 +02:00
..
adff2dff.v
Added adff2dff.v (for techmap -share_map)
2014-08-07 16:14:38 +02:00
blackbox.sed
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
Makefile.inc
Added adff2dff.v (for techmap -share_map)
2014-08-07 16:14:38 +02:00
pmux2mux.v
Added techlibs/common/pmux2mux.v
2014-01-17 20:06:15 +01:00
simcells.v
Renamed $_INV_ cell type to $_NOT_
2014-08-15 14:11:40 +02:00
simlib.v
Renamed $lut ports to follow A-Y naming scheme
2014-08-15 14:18:40 +02:00
techmap.v
Renamed $_INV_ cell type to $_NOT_
2014-08-15 14:11:40 +02:00
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