mirror of https://github.com/YosysHQ/yosys.git
113 lines
2.6 KiB
Verilog
113 lines
2.6 KiB
Verilog
module andor_pmux_basic (
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input [2:0] sel,
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input [5:0] d,
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input a,
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output [2:0] y
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);
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assign y = ({3{sel == 3'd1}} & d[2:0]) |
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({3{sel == 3'd3}} & {d[3] & a, d[4], d[5]}) |
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({3{sel == 3'd6}} & 3'b001);
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endmodule
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module andor_pmux_outer_enable (
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input [2:0] sel,
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input [5:0] d,
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input en,
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output [2:0] y
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);
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wire [2:0] body;
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assign body = ({3{sel == 3'd2}} & {1'b0, d[0], d[1]}) |
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({3{sel == 3'd5}} & {d[2], d[3], d[4]}) |
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({3{sel == 3'd7}} & {d[5], 1'b1, d[0]});
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assign y = {3{en}} & body;
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endmodule
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module andor_pmux_duplicate (
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input [1:0] sel,
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input [11:0] d,
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output [3:0] y
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);
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assign y = ({4{sel == 2'd1}} & d[3:0]) |
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({4{sel == 2'd1}} & d[7:4]) |
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({4{sel == 2'd2}} & d[11:8]);
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endmodule
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module andor_pmux_mixed_select_negative (
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input [1:0] sel_a,
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input [1:0] sel_b,
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input a,
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input b,
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output y
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);
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assign y = ((sel_a == 2'd1) & a) |
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((sel_b == 2'd2) & b);
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endmodule
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module andor_pmux_wide_decode (
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input [3:0] sel,
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input [23:0] d,
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input q,
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output [3:0] y
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);
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assign y = ({4{sel == 4'd1}} & d[3:0]) |
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({4{sel == 4'd4}} & {d[4] & q, d[5], 1'b0, d[6]}) |
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({4{sel == 4'd7}} & d[10:7]) |
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({4{sel == 4'd9}} & {1'b1, d[11], d[12] & q, d[13]}) |
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({4{sel == 4'd12}} & d[17:14]) |
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({4{sel == 4'd15}} & {d[18], d[19], d[20], 1'b1});
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endmodule
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module andor_pmux_shared_subtree (
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input [2:0] sel,
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input [8:0] d,
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input [2:0] q,
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output [2:0] y,
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output [2:0] z
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);
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wire [2:0] sub = ({3{sel == 3'd1}} & d[2:0]) |
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({3{sel == 3'd3}} & d[5:3]);
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assign y = sub | ({3{sel == 3'd6}} & d[8:6]);
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assign z = sub & q;
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endmodule
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module andor_pmux_single_arm_negative (
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input [1:0] sel,
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input [1:0] d,
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output [1:0] y
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);
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assign y = ({2{sel == 2'd1}} & d) | 2'b00;
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endmodule
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module andor_pmux_all_zero_negative (
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input [1:0] sel,
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output [1:0] y
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);
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assign y = ({2{sel == 2'd1}} & 2'b00) |
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({2{sel == 2'd2}} & 2'b00);
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endmodule
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module andor_pmux_non_eq_leaf_negative (
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input [1:0] sel,
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input raw,
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input a,
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input b,
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output y
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);
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assign y = ((sel == 2'd1) & a) |
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(raw & b);
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endmodule
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module andor_pmux_duplicate_complex (
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input [2:0] sel,
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input [11:0] d,
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input q,
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input r,
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output [3:0] y
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);
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assign y = ({4{sel == 3'd2}} & {d[0] & q, d[1], d[2], d[3]}) |
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({4{sel == 3'd2}} & {d[4], d[5] & r, d[6], d[7]}) |
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({4{sel == 3'd5}} & {d[8], d[9] & q, d[10] & r, d[11]});
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endmodule
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