mirror of https://github.com/YosysHQ/yosys.git
39 lines
811 B
Verilog
39 lines
811 B
Verilog
module opt_compact_prefix_yosys_pack (
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input wire [7:0] in_bits,
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output reg [7:0] packed_bits
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);
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integer I;
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integer indx;
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always @* begin
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packed_bits = 8'b0;
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indx = 0;
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for (I = 0; I < 8; I = I + 1) begin
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if (in_bits[I]) begin
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packed_bits[indx] = in_bits[I];
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indx = indx + 1;
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end
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end
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end
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endmodule
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module opt_compact_prefix_yosys_sub (
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input wire [15:0] stall_vec,
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input wire [15:0] payload_vec,
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output reg [15:0] allow_mask
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);
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integer I;
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integer indx;
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always @* begin
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allow_mask = 16'b0;
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indx = 8;
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for (I = 8; I > 0; I = I - 1) begin
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if (stall_vec[I-1]) begin
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allow_mask[I-1] = 1'b0;
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end else begin
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allow_mask[I-1] = payload_vec[indx-1];
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indx = indx - 1;
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end
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end
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end
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endmodule
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