mirror of https://github.com/YosysHQ/yosys.git
49 lines
1.1 KiB
Verilog
49 lines
1.1 KiB
Verilog
module mixed_vector_decode(
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input [2:0] sel0,
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input [2:0] sel1,
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input [3:0] a0,
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input [3:0] b0,
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input [3:0] c0,
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input [3:0] a1,
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input [3:0] b1,
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input [3:0] c1,
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output [3:0] y0,
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output [3:0] y1
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);
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assign {y1, y0} =
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({ {4{sel1 == 3'd1}}, {4{sel0 == 3'd1}} } & {a1, a0}) |
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({ {4{sel1 == 3'd2}}, {4{sel0 == 3'd2}} } & {b1, b0}) |
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({ {4{sel1 == 3'd3}}, {4{sel0 == 3'd3}} } & {c1, c0});
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endmodule
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module partial_vector_decode(
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input [2:0] sel0,
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input [2:0] sel1,
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input [3:0] a0,
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input [3:0] b0,
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input [3:0] c0,
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input [3:0] a1,
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input [3:0] b1,
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input [3:0] c1,
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input [3:0] passthru,
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output [3:0] y0,
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output [3:0] y1
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);
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wire [7:0] stage =
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({ {4{sel1 == 3'd1}}, {4{sel0 == 3'd1}} } & {a1, a0}) |
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({ {4{sel1 == 3'd2}}, {4{sel0 == 3'd2}} } & {b1, b0}) |
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({ {4{sel1 == 3'd3}}, {4{sel0 == 3'd3}} } & {c1, c0});
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assign y1 = stage[7:4];
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assign y0 = stage[3:0] | passthru;
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endmodule
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module tiny_decode(
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input [1:0] sel,
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input a,
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input b,
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output y
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);
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assign y = ((sel == 2'd1) & a) | ((sel == 2'd2) & b);
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endmodule
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