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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 20:12:09 +02:00
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b5f3b70cfeed9421e6d0daa3a1ef968b2b670bc2
yosys/techlibs/intel/max10
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Marcelina Kościelnicka 88e7f90663 Update dff2dffe, dff2dffs, zinit to new FF types.
2020-06-23 18:24:53 +02:00
..
cells_arith.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
cells_map.v
Update dff2dffe, dff2dffs, zinit to new FF types.
2020-06-23 18:24:53 +02:00
cells_sim.v
Clean whitespace and permissions in techlibs/intel
2017-10-05 16:23:49 +02:00
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