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7 lines
155 B
Verilog
7 lines
155 B
Verilog
module abc9_test032(input clk, d, r, output reg q);
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initial q = 1'b0;
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always @(negedge clk or negedge r)
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if (!r) q <= 1'b0;
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else q <= d;
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endmodule
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