yosys/tests/lut/map_or.v at b564fa2e71ab623ccffd16fd0b5cecb80c978aa9 - yosys - Gitea: Git with a cup of tea

luke/yosys

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whitequark 9ef078848a gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

2018-12-05 17:13:27 +00:00

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 module top(...);
     input a, b;
     output y;
     assign y = a|b;
 endmodule