Lofty 75286287c6 Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7 ...

Move rename logic to abc_ops_reintegrate

2026-07-09 08:46:46 +00:00

..

add_sub.ys

End of file fix

2026-06-23 07:23:41 +02:00

adffs.ys

update test

2019-12-03 16:56:15 +01:00

bug5688.ys

tests/arch/gowin: Add wr_en test

2026-02-22 09:00:37 +01:00

compare.v

gowin: Fix X output of $alu techmap

2023-05-01 17:56:41 +02:00

compare.ys

End of file fix

2026-06-23 07:23:41 +02:00

counter.ys

ice40, ecp5, gowin: enable ABC9 by default

2023-11-13 15:28:13 +00:00

dffs.ys

Add some tests

2019-10-21 16:25:15 +02:00

fsm.ys

fix fsm test with proper clock enable polarity

2019-11-11 17:51:26 +01:00

generate_mk.py

Convert gen-tests shell script to python

2026-04-16 11:00:44 +02:00

init-error.ys

gowin: Use dfflegalize.

2020-07-06 12:27:46 +02:00

init.v

attempt to fix formatting

2019-11-25 14:50:34 +01:00

init.ys

ice40, ecp5, gowin: enable ABC9 by default

2023-11-13 15:28:13 +00:00

latches.ys

gowin: add hardware latch support (DL/DLN/DLC/DLP variants)

2026-03-05 16:04:23 +01:00

logic.ys

Move rename logic to abc_ops_reintegrate

2026-06-19 10:46:47 +01:00

lutram.ys

gowin: Fix LUT RAM inference, add more models.

2022-02-09 09:04:34 +01:00

mul_gw1n.ys

gowin: dsp: Add mult inference tests

2026-02-12 14:12:32 +03:00

mul_gw2a.ys

gowin: dsp: Add mult inference tests

2026-02-12 14:12:32 +03:00

mux.ys

Revert "Fix tests due to ABC improvements"

2026-05-11 14:47:08 +02:00

shifter.ys

Add some tests

2019-10-21 16:25:15 +02:00

tribuf.ys

End of file fix

2026-06-23 07:23:41 +02:00